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WCDMA Quasi-Direct Modulator
with VGA and PA Driver
Pin Description (continued)
PIN
20
21
22
23
26
27
28
—
NAME
V CC _VCO
GND_VCO
VTUNE
BYP
CS
SDATA
SCLK
EP
FUNCTION
Supply for VCO. Bypass to system ground with a capacitor as close to the pin as possible. Do not
share ground vias for the bypass capacitor with any other branch (see the Typical Operating Circuit ).
RF VCO Varactor Ground. Connect to the ground at the PLL loop-filter capacitors. Do not connect to
the exposed pad.
Oscillator-Frequency Tuning Voltage Input
Bypass with a Capacitor to GND. The capacitor is used by the on-chip VCO voltage regulator (see
the Typical Operating Circuit ).
3-Wire Serial Bus Enable Input (Figure 1)
3-Wire Serial Bus Data Input (Figure 1)
3-Wire Serial Bus Clock Input (Figure 1)
Exposed Pad. Connect to the ground plane for proper heat dissipation.
Detailed Description
The MAX2395 quasi-direct modulator accepts differen-
tial I/Q baseband inputs with external common-mode
bias. A gain-control voltage pin (VGC) controls the gain
of the IF and RF VGAs simultaneously to achieve the
best current consumption and linearity performance.
GmC Filters
The internal GmC filters are used to eliminate noise and
baseband DAC aliasing signals above 8MHz. The GmC
filter can be bypassed (GMC_EN bit, OPCTRL register bit
3), lowering the total current at the expense of no filtering.
To speed up the settling time when transitioning from
IDLE to transmit mode, the filter can be forced to stay
active in IDLE mode using the IDLE_PRG bit (OPCTRL
register bit 1). Contact factory if bypass mode is used.
I/Q Modulator
Differential in-phase (I) and quadrature-phase (Q) input
pins are designed to be DC-coupled and biased with
the baseband output from a digital-to-analog converter
(DAC). The I_ and Q_ inputs need a DC bias, which
can range from 1.35V to 1.65V. The current draw is
negligible and the differential input capacitance is 4pF.
The VCO frequency is divided by 6 to produce the RF
I/Q LO signals.
IF/RF VGA
The part offers approximately 90dB of gain-control
range. An external voltage must be applied using a
DAC allowing for dynamic gain control. To minimize the
noise contribution from the DAC to the RF signal, place
an RC filter at this pin (refer to the MAX2395 Evaluation
Kit data sheet). The PA driver is included in the RF
VGA.
Internal VCO and Tank
The integrated monolithic VCO and tank is tuned
through the VTUNE pin. The RF/IF LO signals are gen-
erated from this oscillator.
PLL
The internal PLL uses a charge-pump output to drive a
loop filter. The loop filter is typically a passive 2nd-
order lead lag filter with a bandwidth of 10kHz. The
loop filter must be optimized for a selected charge-
pump current, where K VCO = 90MHz/V. The internal
architecture requires the RF VCO to run at 1.2x the
desired frequency, mandating a 240kHz comparison
frequency for an output step size of 200kHz. The LD
output indicates whether the PLL is locked. An output
high indicates a lock condition.
There is an optional frequency doubler at the input of
the PLL reference divider. When using a 13MHz refer-
ence frequency, either a 40kHz comparison can be
used or the internal frequency doubler is enabled to
allow a comparison frequency of 80kHz. The optional
frequency double can be activated by setting OPCTRL
register bit 7 = 1.
PA Driver/RF Upconverter
The IF signal is upconverted with an image reject RF
mixer, and differentially fed into the PA driver. The PA
driver converts differential input signals to a single-
ended output. The driver requires a pullup inductor,
which is part of the output matching network.
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